drf1202 500v, 50a, 30mhz the drf1202 hybrid includes a high power gate driver and the power mosfet. the driver output can be con gured as inverting and non- inverting. it was designed to provide the system designer increased exibility and lowered cost over a non-integrated solution. typical applications ? class c, d and e rf generators ? switch mode power ampli ers ? pulse generators ? ultrasound transducer drivers ? acoustic optical modulators features ? switching frequency: dc to 15mhz ? low pulse width distortion ? single power supply ? 1v cmos schmitt trigger input 1v hysteresis ? inverting non-inverting select ? rohs compliant ? switching speed 3-4ns ? b vds = 500v ? i ds = 50a avg. ? r ds(on) .25 ohm ? p d = 1180w symbol parameter ratings unit v dd supply voltage 15 v in, fn input single voltages -.7 to +5.5 i o pk output current peak 8a t jmax operating and storage temperature 175 c mosfet driver hybrid driver absolute maximum ratings driver speci cations symbol parameter min typ max unit v dd supply voltage 10 15 v in input voltage 3 5.5 in (r) input voltage rising edge 3 ns in (f) input voltage falling edge 3 i ddq quiescent current 2ma i o output current 8a c iss input capacitance 3 r in input parallel resistance 1m v t(on) input, low to high out (see truth table) 0.8 1.1 v v t(off) input, high to low out (see truth table) 1.9 2.2 t dly time delay (throughput) 38 ns t r rise time 5 ns t f fall time 5 t d prop. delay 35 microsemi website - http://www.microsemi.com 050-4973 rev d 5-2011 d s in driver 50a mosfet
drf1202 mosfet absolute maximum ratings symbol parameter min typ max unit bv dss drain source voltage 500 v i d continuous drain current t hs = 25c 50 a r ds(on) drain-source on state resistance 0.25 t jmax operating temperature 175 c mosfet dynamic characteristics symbol parameter min typ max unit c iss input capacitance 2000 pf c oss output capacitance 165 c rss reverse transfer capacitance 75 mosfet thermal characteristics symbol parameter min typ max unit r jc thermal resistance junction to case 0.53 c/w r jhs thermal resistance junction to heat sink 0.141 t jstg storage temperature -55 to 150 c p dhs maximum power dissipation @ t sink = 25c 1060 w p dc total power dissipation @ t c = 25c 2830 microsemi reserves the right to change, without notice, the speci cations and information contained herein. 050-4973 rev d 5-2011 figure 1, drf1202 simpli ed circuit diagram the simpli ed drf1202 circuit diagram is illustrated above. by including the driver high speed by-pass capacitor (c1), their contributio n to the internal parasitic loop inductance of the driver output is greatly reduced. this, coupled with the tight geometry of the h ybrid, allows optimal gate drive to the mosfet. this low parasitic approach, coupled with the schmitt trigger input (in), kelvin signal ground (sg) and the anti- ring function, provide improved stability and control in kilowatt to multi-kilowatt, high frequency applications. the in pin i s the input for the control signal and is applied to a schmitt trigger. both the fn and in pins are referenced to kelvin ground (sg.) the signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed speci cally for the ring abatement. the power drivers provide high current to the gate of the mosfets. symbol parameter min typ max unit c out output capacitance 2500 pf r out output resistance .8 l out output inductance 3 nh f max operating frequency cl = 3000nf + 50 30 mhz f max operating frequency rl = 50 50 driver output characteristics symbol parameter min typ max unit r jc thermal resistance junction to case 1.5 c/w r jhs thermal resistance junction to heat sink 2.5 t jstg storage temperature -55 to 150 c p djhs maximum power dissipation @ t sink = 25c 60 w p djc total power dissipation @ t c = 25c 100 driver thermal characteristics
the function (fn, pin 3) is the invert or non-invert select pin, it is internally held high. drf1202 050-4973 rev d 5-2011 the test circuit illustrated above was used to evaluate the drf1202 (available as an evaluation board drf12xx / evalsw.) the i nput control signal is applied to the drf1202 via in(4) and sg(5) pins using rg188. this provides excellent noise immunity and cont rol of the signal ground currents. the +v dd inputs (2,6) are by-passed (c1,c2, c4-c9), this is in addition to the internal by-passing mentioned previously. the capacitor s used for this function must be capable of supporting the rms currents and frequency of the gate load. r l set for i dm at v ds max this load is used to evaluate the output performance of the drf1202. figure 2, drf1202 test circuit truth table *referenced to sg fn (pin 3)* in (pin 4)* mosfet high high on high low off low high off low low on
figure 3, drf1202 mechanical outline all dimensions are .005 drf1202 050-4973 rev d 5-2011 pin assignments pin 1 ground pin 2 +vdd pin 3 fn pin 4 in pin 5 sg pin 6 +vdd pin 7 ground pin 8 source pin 9 drain pin 10 source
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